? semiconductor components industries, llc, 2006 august, 2006 ? rev. 1 1 publication order number: IRF830/d IRF830 power field effect transistor n ? channel enhancement mode silicon gate tmos this tmos power fet is designed for high voltage, high speed power switching applications such as switching regulators, converters, solenoid and relay drivers. ? silicon gate for fast switching speeds ? low r ds(on) to minimize on ? losses, specified at elevated temperature ? rugged ? soa is power dissipation limited ? source ? to ? drain diode characterized for use with inductive loads maximum ratings rating symbol value unit drain ? source voltage v dss 500 vdc drain ? gate voltage (r gs = 1.0 m ) v dgr 500 vdc gate ? source voltage v gs 20 vdc drain current continuous, t c = 25 c continuous, t c = 100 c peak, t c = 25 c i d 4.5 3.0 18 adc total power dissipation @ t c = 25 c derate above 25 c p d 75 0.6 watts w/ c operating and storage temperature range t j , t stg ? 55 to 150 c thermal characteristics thermal resistance ? junction ? to ? case ? junction ? to ? ambient r jc r ja 1.67 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 5 seconds t l 300 c see the mtm4n45 data sheet for a complete set of design curves for the product on this data sheet. design curves of the mtp4n45 are applicable for this product. tmos power fet 4.5 amperes, 500 volts r ds(on) = 1.5 device package shipping ordering information IRF830 to ? 220ab 50 units/rail to ? 220ab case 221a style 5 1 2 3 4 pin assignment 1 2 3 source gate drain 4 drain http://onsemi.com ? n ? channel d s g
IRF830 http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted) characteristic symbol min max unit off characteristics drain ? to ? source breakdown voltage (v gs = 0 vdc, i d = 0.25 madc) v (br)dss 500 ? vdc zero gate voltage drain current (v ds = rated v dss , v gs = 0 vdc) (v ds = 0.8 rated v dss , v gs = 0 vdc, t j = 125 c) i dss ? ? 0.2 1.0 madc gate ? body leakage current, forward (v gsf = 20 vdc, v ds = 0) i gss(f) ? 100 nadc gate ? body leakage current, reverse (v gsr = 20 vdc, v ds = 0) i gss(r) ? 100 nadc on characteristics (1) gate threshold voltage (v ds = v gs , i d = 0.25 ma) v gs(th) 2.0 4.0 vdc static drain ? to ? source on ? resistance (v gs = 10 vdc, i d = 2.5 adc) r ds(on) ? 1.5 ohm on ? state drain current (v gs = 10 v) (v ds 6.75 vdc) i d(on) 4.5 ? adc forward transconductance (v ds 6.75 vdc, i d = 2.5 adc) g fs 2.5 ? mhos dynamic characteristics input capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 800 pf output capacitance c oss ? 200 reverse transfer capacitance c rss ? 60 switching characteristics (1) turn ? on delay time (v dd = 200 vdc, i d = 2.5 apk, r g = 15 ) t d(on) ? 30 ns rise time t r ? 30 turn ? off delay time t d(off) ? 55 fall time t f ? 30 total gate charge (v ds = 0.8 rated v dss , v gs = 10 vdc, i d = rated i d ) q g 22 (typ) 30 nc gate ? source charge q gs 12 (typ) ? gate ? drain charge q gd 10 (typ) ? source ? drain diode characteristics (1) forward on ? voltage (i s = rated i d , v gs = 0) v sd 1.1 (typ) 1.6 vdc forward turn ? on time t on limited by stray inductance reverse recovery time t rr 450 (typ) ? ns internal package inductance internal drain inductance (measured from the contact screw on tab to center of die) (measured from the drain lead 0.25 from package to center of die) l d 3.5 (typ) 4.5 (typ) ? ? nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s 7.5 (typ) ? (1) pulse test: pulse width 300 s, duty cycle 2%.
IRF830 http://onsemi.com 3 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 ??? 1.15 ??? z ??? 0.080 ??? 2.04 q h z l v g n a k 123 4 d seating plane ? t ? c s t u r j to ? 220ab case 221a ? 09 issue z style 5: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 IRF830/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative e ? fet is a trademark of semiconductor components industries, llc. tmos is a registered trademark of semiconductor components industries, llc.
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